1. Field of the Invention
The present invention relates to a method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Furthermore, the invention is also concerned with a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. Moreover, the invention is also directed to the provision of an electronic package incorporating a substrate, particularly such as in a flip chip arrangement, wherein the substrate is to be joined to a silicon semiconductor chip or wafer, which may be subject to the formation of scratches and cracks, and wherein novel measures are taken to prevent the formation or propagation of the scratches and/or cracks in the backside of the chip.
In essence, the backsides of silicon chips or wafers are occasionally subjected to the forming of scratches on the backside surfaces during fabrication or processing. These scratches may be caused by the polishing, milling or grinding of the backside of the respective silicon chip or wafer, such as for example, by means of a grinding process, wherein the surface finishing is accomplished by either numerically controlled milling machines, which may be followed by a manual polishing, various chemical and mechanical polishing compositions or slurries, or wet etching and the like procedures which are intended to remove the machine milling or fabrication marks and scratches.
Moreover, there is also the possibility that scratches or cracks may be formed on the backside of the silicon chip or wafer during the process of joining the latter to a substrate at high temperatures, such as during reflow, whereby during subsequent of the joined cooling components, the silicon chip tends to shrink a lesser amount than the substrate, due to a higher coefficient of thermal expansion (CTE) being present for the substrate in comparison with that of the silicon chip. This differential in shrinkage generates high tensile stresses during thermal cycling in the backside of the silicon chip or wafer tending to cause the formation of microcracks in the silicon chip at the locations of existing minute scratches. Consequently, it is imperative that steps be taken to prevent the cracks propagating from the backside scratches on the silicon chip or wafer towards the front surface thereof, whereby such scratches can be nucleation sites for the cracks during package fabrication or thermal cycling, and which may cause package failure if propagating to the front side of the silicon chip or wafer, which represents the electronic device region of the electronic package incorporating the electrical contacts and circuitry, by a potential short-circuiting thereof.
2. Discussion of the Prior Art
Various methods and devices are currently known in the technology, which are adapted in diverse modes to inhibit or restrict the formation of scratches and propagation of microcracks in which the surfaces, and particularly the backside surfaces of semiconductor chips or wafers, which may be constituted of a silicon (Si) material.
Chang, et al., U.S. Pat. No. 6,887,793 B2, disclose a method for plasma etching a wafer subsequent to the backside grinding thereof, and wherein this etching is adapted to remove a photoresist coating layer present on the wafer surface. The method disclosed in this patent, has nothing in common with the chip or wafer backside treatment analogous to the present invention in preventing the formation of scratches or propagation of cracks in the backside of the wafer or chip.
Peterson, et al. U.S. Pat. No. 6,844,623 B1 disclose the application of a temporary coating for the protection of a microelectronic device wherein the coating is applied to a wafer surface and thereafter removed. This has no bearing on the method of treatment for protection of the backside of a semiconductor wafer or chip in a manner analogous to the present invention, which is adapted to either inhibit the formation of cracks or scratches or the propagation of cracks in the silicon wafer or chip.
Hendrix, et al., U.S. Pat. No. 6,514,835 B1 provide for a stress control method for thin films due to mechanical deformation of wafer substrates. Again, this has nothing in common with the inventive methods of protecting the backside of a silicon semiconductor chip or wafer from the formation or propagation of scratches and cracks, which could potentially adversely influence the integrity of an electronic package utilizing the wafer or chip.
Kane, et al., U.S. Pat. No. 6,790,125 B2 disclose an arrangement for finishing the backside of a wafer or chip by means of a milling machine, and wherein a subsequent polishing or wet etching method is employed to remove machine milling marks and scratches. The foregoing has nothing in common with the present inventive method of protecting the backside of a silicon wafer or chip from the deleterious effects of scratches and cracks which may be present therein, or which have a tendency to substantially propagate internally of the wafer or chip.
Finally, Maurice, et al., U.S. Patent Publication No. 2004/0241461 A1 discloses a method of protecting the back surface of a wafer by the application thereon of a capping layer thereon during the handling of the wafer. Again, this type of application of the capping layer is different from and has nothing in common with the method of protecting the backside of the wafer or chip pursuant to the present invention.
Accordingly, in order to prevent the formation of backside cracks or the propagation of cracks formed in the backside of a wafer or chip during processing thereof, pursuant to the invention, alternative methods may be utilized, which present significant advantages over the current state of the technology.